Units: 5 (3 Lecture/2 Laboratory)
Prerequisite: EEC 18 or EEC 180A
Catalog Description: Computer-aided design of digital systems with emphasis on hardware description languages, logic synthesis, and field-programmable gate arrays (FPGA). May cover advanced topics in digital system design such as static timing analysis, pipelining, memory system design, and testing digital circuits.
ABET Student Outcomes:
1) The students will be able to:
a) Describe combinational and sequential logic in Verilog
b) Describe a design using behavioral and structural code
c) Develop testbenches to verify correctness of designs
d) Design and verify complex designs using Verilog and CAD tools
e) Design complex systems using FPGAs
2) Students who have completed this course should have achieved:
a) Student Outcome 1: an ability to identify, formulate, and solve complex engineering problems by applying principles of engineering, science, and mathematics.
b) Student Outcome 2: an ability to apply engineering design to produce solutions that meet specified needs with consideration of public health, safety, and welfare, as well as global, cultural, social, environmental, and economic factors.
c) Student Outcome 6: an ability to develop and conduct appropriate experimentation, analyze and interpret data, and use engineering judgment to draw conclusions.
Expanded Course Description:
I. Review of basic topics in logic design
A. Boolean Algebra
B. Combinational Logic Design and Optimization
C. Flip-flops and Latches
D. Sequential Logic Design and optimization
II. Hardware Description Language
A. Structural modeling
B. Simulation Cycle
C. Modeling data
D. Register-Transfer Level (RTL) modeling
III. Computer-aided design of digital circuits
A. Design Flow
B. Functional Simulation
C. Overview of logic synthesis and technology mapping
D. Timing Simulation
IV. Field Programmable Gate Arrays
A. Architecture of FPGA
B. Programmable logic blocks and Programmable interconnect schemes
C. FPGA-based design flow
V. Timing Analysis and Clocking Schemes
A. Static timing analysis concepts
B. Edge-triggered flip-flops
C. Level-sensitive latches
VI. Design Implementation and Optimization
A. Control/Data Separation
B. Pipelining
C. Retiming
VII. Memory System Design
A. SRAM
B. DRAM
C. Interfacing Memory to a Microprocessor Bus
VIII. Advanced Topics (Optional)
A. Processor Design
B. Arithmetic Circuit Design
C. Hardware Testing and Design for Testability
