Master’s Thesis Award Honors Alum for Ultrafast, Energy-Efficient Processing Framework

For a processing framework that achieved a 32 million-times improvement in speed and energy efficiency over NVIDIA when considering chip area, Sagar Sajeev, M.S. ’25, has received the Jeffery C. Gibeling Master’s Thesis Excellence Award from the College of Engineering at the University of California, Davis.

The annual award recognizes the master's student who submitted the best thesis, as well as the mentorship of their major professor. It honors Professor Emeritus of Materials Science and Engineering Jeffery Gibeling, who served as the college's interim dean in 2021 and provided invaluable service to graduate students over his 37-year career.

An electrical and computer engineering master’s student under Professor Bevan Baas, Sajeev explored regular expressions on fine-grain many-core processor arrays in his research. Baas’ lab is well known for these types of processors, having designed and fabricated four generations in silicon.

“Professor Baas gave me the freedom to explore my ideas while guiding me toward a clear and rigorous research direction, and his mentorship helped me grow as both a researcher and an engineer,” Sajeev said.

Regular expressions, or RegEx, help a computer find patterns in a data set, such as all words that begin with “C," and are essential in data validation, cybersecurity and AI-related data processing workflows. Fine-grain many-core processor arrays embody the idea of strength in numbers: many, if not thousands, of minuscule processors work in parallel to tackle complicated tasks that larger computer processing units may struggle to handle.

While there has been significant research in both RegEx and fine-grain multi-processor arrays, little to no research has combined the two. Sagar’s integrative approach works because RegEx reinforces the main strength of using many parallel processors. The pattern recognition can be spread across many processing cores, offloading the burden and expediting computations.

“The idea is to break a complex search pattern into smaller pieces and assign each piece to a different core,” Sajeev said. “Each core handles one part of the pattern, and together they work like a pipeline to find the full match.”

This kind of architecture is what Sajeev called the “snake chain.” Each core implements a specific subtask and communicates with neighboring cores rather than all other cores simultaneously.

To achieve this architecture, Sajeev developed a RegEx processing framework for the many-core platform. A key component of his framework is the Pattern Code Generation Tool, or PCGT, which he developed from the ground up. The tool parses regular expressions, identifies their component symbols, and generates the C++ kernels and configuration files needed to execute them across the many-core processors.

His design demonstrates that fine-grain many-core processing architectures can be highly effective for data-intensive workloads. Moreover, the design’s high-energy efficiency stands to greatly benefit AI tools and data centers, accelerating innovation while decreasing energy use.

“Compared with traditional processors, the improvements ranged from millions to even billions of times when combining performance, energy efficiency and chip area,” Sajeev said, referencing technological leaders like NVIDIA, Intel and AMD. 

On receiving the Gibeling Award, Sajeev described it as a full-circle moment. When he first arrived at UC Davis, he attended an orientation event where graduate students were recognized for their research. He said he would often wonder if he could ever reach that level. Now, he said, he knows he can.

He dedicates his Gibeling Award to his father, who passed away a few months after Sagar arrived in Davis from India. His father was his role model and one of his greatest sources of inspiration, and Sagar says his values continue to guide him. To honor his father through this award means the world to him.

“It means more than the award itself,” he said.

Following graduation, Sajeev joined cPacket, a computer hardware manufacturer in Milpitas, California. He works as a field programmable gate array engineer, building on the innovation with chips he achieved as a master’s student.