Professor Houman Homayoun and Najmeh Nazari, from the ASEEC lab at ECE UC Davis, created a curriculum to design hardware accelerators by taking advantage of Intel's DevCloud, a cloud based solution for Data Center to Edge Workloads focusing on accelerating artificial intelligence and machine learning applications. Intel selected this curriculum a as a Third-Party Training Module for academics and industry user for training purposes. The UC Davis curriculum provides a set of educational tutorials and labs for senior undergraduate and graduate level courses using DPC++ and Intel CloudDev to overcome the challenges of parallel programming, as well as programmability and adaptation of FPGA hardware programming for end-user. The repository on the GitHubis publicly available and includes a set of realistic, practical and popular workloads to demonstrate the benefits of DCP++ and DevCloud for accelerating compute intensive kernels. Moreover, the curriculum provides a comprehensive performance bottleneck analysis using Intel VTune and along with guidelines on design optimization strategies. Finally, a set of graduate and senior undergraduate level lectures, videos, slides, and tutorials from beginner to advanced level on how to generate hardware using Intel oneAPI toolkit is are available online. The ECE department is eagerly makes available such course materials for use by other universities and companies and we appreciate the support from Intel in this effort.
Please click below for a video playlist of the Labs: